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SQ3585EV-T1_GE3
+NomenclatureMOSFET N/P-CH 20V 6TSOP
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FabricantSiliconix
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Pièce fabricant #SQ3585EV-T1_GE3
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Fiche technique SQ3585EV-T1_GE3 DataSheet
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Package TSOT-23-6
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En stock23661
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Spécifications
| Attribut | Valeur |
| Supplier | Vishay Siliconix |
| Package / Case | Tape & Reel (TR),Cut Tape (CT) |
| Series | Automotive, AEC-Q101, TrenchFET® |
| Part Status | Active |
| FET Type | N and P-Channel |
| FET Feature | Standard |
| Drain to Source Voltage (Vdss) | 20V |
| Current - Continuous Drain(Id) @ 25°C | 3.57A (Tc), 2.5A (Tc) |
| Rds On(Max) @ Id Vgs | 77mOhm @ 1A, 4.5V, 166mOhm @ 1A, 4.5V |
| Vgs(th)(Max) @ Id | 1.5V @ 250µA |
| Gate Charge(Qg)(Max) @ Vgs | 2.5nC @ 4.5V, 3.5nC @ 4.5V |
| Power - Max | 1.67W |
| Operating Temperature | -55°C ~ 175°C (TJ) |
| Mounting Type | Surface Mount |
Présentation
Description
Equivalent
Features
1. Voltage Rating: The device is designed to handle specific voltage levels, ensuring suitable operation within specified limits.
2. Current Capacity: It supports a particular maximum current, critical for managing power delivery in circuits.
3. On-Resistance: The FET will have a specific on-resistance, affecting efficiency and heat generation.
4. Package Type: This component is likely housed in a specific package style, which affects its mounting and thermal characteristics.
5. Thermal Performance: The device will have defined thermal limits, indicating how much heat it can dissipate safely.
6. Switching Speed: The FET's speed, important for applications requiring rapid on/off cycling.
7. Gate Charge: This affects the power required to drive the FET, relevant for efficiency considerations.
For precise specifications, consulting the manufacturer's datasheet is recommended, as it provides detailed and authoritative information.
Pinout
Each of the two MOSFETs within the package is used for controlling power or signal levels. The pin configuration generally includes:
1. Pins 1, 2, 3 (Source 1): Source connection for the first MOSFET.
2. Pin 4 (Gate 1): Gate connection for the first MOSFET.
3. Pins 5, 6, 7 (Source 2): Source connection for the second MOSFET.
4. Pin 8 (Gate 2): Gate connection for the second MOSFET.
5. The back of the package often acts as the Drain for both transistors.
For precise pin configuration and functions, consulting the official datasheet is recommended.