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HMC7043LP7FE
+NomenclatureIC FRACT-N PLL W/SWEEPR 48LFCSP
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FabricantAnalog Equipment GmbH.
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Pièce fabricant #HMC7043LP7FE
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Fiche technique HMC7043LP7FE DataSheet
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Package QFN-48
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En stock6506
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Spécifications
| Attribut | Valeur |
| Package | Strip |
| ProductStatus | Active |
| PLL | Yes |
| Input | Clock |
| Output | CML, LVDS, LVPECL |
| NumberofCircuits | 1 |
| Ratio-Input:Output | 1:14 |
| Differential-Input:Output | Yes/Yes |
| Frequency-Max | 3.2GHz |
| Divider/Multiplier | Yes/No |
| Voltage-Supply | 3.135V ~ 3.465V |
| OperatingTemperature | -40°C ~ 85°C |
| MountingType | Surface Mount |
| Package/Case | 48-VFQFN Exposed Pad, CSP |
Présentation
Description
Key features:
- Inputs: Supports up to 4 differential/single-ended inputs (LVDS, LVPECL, HCSL, CMOS).
- Outputs: 14 configurable outputs (up to 3.2 GHz) with programmable formats (LVDS, LVPECL, HCSL, CMOS).
- Jitter Performance: Sub-100 fs RMS jitter (12 kHz–20 MHz).
- Flexibility: On-chip VCO, SPI control, and synchronization options.
- Package: 72-lead LFCSP (10 mm × 10 mm).
Applications include 5G radios, test equipment, and high-speed digital systems requiring precise timing.
For detailed specs, refer to the datasheet.
Equivalent
- AD9528 (Analog Devices)
- LMK04828 (Texas Instruments)
- Si5345 (Silicon Labs)
These offer similar features like low jitter, multiple outputs, and phase synchronization. Check datasheets for exact compatibility.
Features
- Frequency Synthesis: Generates output frequencies up to 3 GHz with ultra-low jitter (<100 fs RMS).
- Input Flexibility: Supports multiple input sources (LVDS, LVPECL, HCSL, CMOS) and frequencies (8 kHz to 1.5 GHz).
- Outputs: 14 configurable outputs (LVPECL, LVDS, or CMOS) with independent frequency/phase control.
- Jitter Attenuation: Integrated PLL with <1 ps RMS additive jitter for noise filtering.
- Redundancy & Sync: Supports automatic or manual input switching and deterministic synchronization.
- Low Power: Operates at 3.3 V with power-saving modes.
- Package: 72-lead LFCSP (7x7 mm).
Ideal for high-speed data converters, wireless infrastructure, and FPGA clocking.