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IC INVERTER 6CH 1-INP 14SO
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FabricantNexperia USA Inc.
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Pièce fabricant #74HC04D,653
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En stock7745
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Spécifications
| Attribut | Valeur |
| Supplier | Nexperia USA Inc. |
| Package / Case | Tape & Reel (TR),Cut Tape (CT) |
| Series | 74HC |
| Part Status | Active |
| Logic Type | Inverter |
| Number of Circuits | 6 |
| Number of Inputs | 1 |
| Voltage - Supply | 2V ~ 6V |
| Current - Quiescent (Max) | 2 µA |
| Current - Output High Low | 5.2mA, 5.2mA |
| Logic Level - Low | 0.5V ~ 1.8V |
| Logic Level - High | 1.5V ~ 4.2V |
| Max Propagation Delay @ V Max CL | 14ns @ 6V, 50pF |
| Operating Temperature | -40°C ~ 125°C |
| Mounting Type | Surface Mount |
| Supplier Device Package | 14-SO |
Présentation
Description
Package note: The D suffix denotes a specific packaging variant (eg, SOIC/DIP style). Typical pins (DIP-14): Vcc = pin 14, GND = pin 7. Inputs are on pins 1,3,5,9,11,13 and outputs on pins 2,4,6,8,10,12.
Electrical basics (at 4.5–5.5 V typical):
- Vcc range: about 2–6 V
- VIH ≈ 0.7 Vcc, VIL ≈ 0.3 Vcc
- Output drive: a few milliamps per gate
- Propagation delay: roughly 8–25 ns at 5 V (depends on vendor)
- Input leakage: microampere range
Applications: simple digital inversion, buffering, and timing/oscillator circuits (use RC networks carefully).
652/653 or similar suffixes are usually date/lot or packaging codes and do not affect operation; verify exact variant in the datasheet. Always use proper decoupling (0.1 µF) near Vcc. Do not tie outputs together.
Equivalent
- 74HC04, 74HCT04 (TTL-input compatibility)
- 74AC04 / 74ACT04
- 74LVC04 (and variants like 74LVX04)
Drop-in D-pack variants (same function): SN74HC04D (TI), MC74HC04D (Onsemi), 74HC04D (NXP/Nexperia/ST). Note: use 74HCT04 for TTL-level compatibility; other families differ in speed/voltage ranges.
Pinout
- Function: Hex inverter — six independent NOT gates (A→Y): 1A→1Y, 2A→2Y, 3A→3Y, 4A→4Y, 5A→5Y, 6A→6Y.
Manufacturer
Application
- 74HC653: Octal D-type latch/register with 3-state outputs (bus-friendly). Applications – temporary data storage and transfer on bidirectional buses, I/O expansion for microcontrollers, demultiplexing address/data lines on multiplexed buses, memory-mapped I/O interfaces, and bus buffering/ISOLATION for display drivers.