Part A
AT25SF161B-SSHB-T
Technologie adesto
- Lifecycle
- Active
- Stock
- 3214 PCS
- Package
- SOIC-8
- Series
- Mémoire
Replacement verdict
Compatible functional replacement candidate
The AT25SF161B-SSHB-T is a functionally compatible replacement candidate for the AT25SF321B-SSHB-T, as both devices share an identical package, pinout, supply voltage range, and SPI interface, with the primary distinction being the halved memory density of the AT25SF161B. Designers must confirm that the reduced 16-Mbit capacity satisfies firmware and data-logging requirements before substituting.
Memory Density
Not compatible
Package Type
High match
Supply Voltage Range
High match
Interface Type
High match
Parts at a glance
Part B
AT25SF321B-SSHB-T
Technologie adesto
- Lifecycle
- Active
- Stock
- 4695 PCS
- Package
- SOIC-8
- Series
- Mémoire
Key differences
Rows are prioritized by design impact. Highlighted values require attention during substitution.
Key electrical and mechanical differences between the two devices
| Parameter | AT25SF321B-SSHB-T | AT25SF161B-SSHB-T | Why it matters |
|---|---|---|---|
| Density / Memory Size | 32 Mbit (4 MB) | 16 Mbit (2 MB) | The total storage capacity determines whether the device can hold the required firmware image, configuration data, or logs; a 16 Mbit part cannot substitute for a 32 Mbit part if the image exceeds 2 MB. |
| Memory Organization | 4,096 sectors x 4 Kbit; 512 blocks x 64 Kbit; 64 blocks x 512 Kbit | 4,096 sectors x 4 Kbit; 256 blocks x 64 Kbit; 32 blocks x 512 Kbit | Sector and block granularity affects erase/program operations and file-system layout; matching 4 Kbit sector size preserves erase timing and wear-leveling behavior between the two parts. |
| Interface Type | SPI / Dual SPI / Quad SPI (QSPI) | SPI / Dual SPI / Quad SPI (QSPI) | The bus protocol must match the host controller; both support standard, dual, and quad SPI, so the interface is functionally interchangeable. |
| Supply Voltage Range | 2.7 V to 3.6 V | 2.7 V to 3.6 V | Operating voltage must be compatible with the system rail; identical 2.7–3.6 V range means both parts work in the same 3.3 V designs. |
| Maximum Clock Frequency | 104 MHz | 104 MHz | Clock rate determines read/program throughput; matching 104 MHz ensures the same timing budget and controller configuration can be reused. |
| Package / Mounting | 8-SOIC (0.154 in, 3.90 mm width), surface mount | 8-SOIC (0.154 in, 3.90 mm width), surface mount | Package footprint and pinout must match the PCB land pattern; identical 8-SOIC packages allow drop-in board replacement without layout changes. |
| Operating Temperature Range | -40 °C to +85 °C | -40 °C to +85 °C | Temperature rating must cover the application environment; identical industrial range means both parts suit the same operating conditions. |
| Page Size | 256 bytes per page | 256 bytes per page | Page size sets the maximum bytes per program operation; matching 256-byte pages keeps write routines and buffer sizing identical between the parts. |
| Endurance | 100,000 program/erase cycles per sector | 100,000 program/erase cycles per sector | Endurance defines the write-cycle lifetime; identical 100k-cycle rating means both parts offer the same reliability for frequently updated data. |
| Data Retention | 20 years | 20 years | Retention guarantees how long stored data remains valid without power; matching 20-year retention supports the same long-life product requirements. |
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Full specification comparison
Use manufacturer datasheets as the final authority.
| Specification | AT25SF161B-SSHB-T | AT25SF321B-SSHB-T |
|---|---|---|
| Part Status | Active | Active |
| Memory Type | Non-Volatile | Non-Volatile |
| Memory Format | FLASH | FLASH |
| Technology | FLASH - NOR | FLASH - NOR |
| Memory Size | 16Mb (2M x 8) | 32Mb (4M x 8) |
| Memory Interface | SPI - Quad I/O | SPI - Quad I/O |
| Clock Frequency | 108 MHz | 108 MHz |
| Write Cycle Time - Word Page | 50µs, 2.4ms | 50µs, 3ms |
| Voltage - Supply | 2.7V ~ 3.6V | 2.7V ~ 3.6V |
| Operating Temperature | -40°C ~ 85°C (TA) | -40°C ~ 85°C (TA) |
| Mounting Type | Surface Mount | Surface Mount |
Frequently asked questions
What are the key differences between the AT25SF321B-SSHB-T and AT25SF161B-SSHB-T?
The primary difference is memory density: the AT25SF321B-SSHB-T provides 32 Mbit (4 MB) of SPI NOR flash, while the AT25SF161B-SSHB-T provides 16 Mbit (2 MB). Both are part of the Adesto (now Renesas) AT25SF series, offered in the same 8-lead SOIC (0.150" body) package and specified for the same supply voltage range and SPI interface, so the main selection criterion is the required code/data storage capacity.
Are the AT25SF321B-SSHB-T and AT25SF161B-SSHB-T pin-compatible?
Yes. Both devices use the standard 8-lead SOIC (208-mil) footprint with the same pinout: /CS, DO (IO1), /WP (IO2), GND, DI (IO0), CLK, /HOLD (IO3), and VCC. Because the package and pin functions match, the AT25SF161B-SSHB-T can typically be replaced by the AT25SF321B-SSHB-T on an existing PCB without layout changes, provided the host firmware supports the larger density.
Do both devices support the same SPI interface modes?
Yes. Both the AT25SF321B-SSHB-T and AT25SF161B-SSHB-T support standard SPI, Dual SPI, and Quad SPI operation, with clock frequencies up to 104 MHz for standard read commands and up to 104 MHz for Quad I/O reads. They also support the same command set architecture, including JEDEC ID read, page program, sector/block erase, and chip erase operations.
What is the operating voltage and temperature range for these devices?
Both the AT25SF321B-SSHB-T and AT25SF161B-SSHB-T operate from a single 2.7 V to 3.6 V supply and are specified over the industrial temperature range of -40 °C to +85 °C. These parameters are common across the AT25SF series and should be confirmed against the respective Renesas datasheets for the exact revision in use.
Can the AT25SF161B-SSHB-T be substituted with the AT25SF321B-SSHB-T in an existing design?
Substitution is generally feasible because both parts share the same package, pinout, voltage range, and SPI command architecture. However, the host firmware must be able to address the larger 32 Mbit address space of the AT25SF321B-SSHB-T, and any density-dependent parameters such as sector erase size, page size, and JEDEC ID must be validated. The design should be verified against the AT25SF321B datasheet before production release.
What are the erase sector and block sizes for these devices?
Both devices are organized with a 256-byte page size and support 4 KB sector erase, 32 KB block erase, 64 KB block erase, and full chip erase commands. The larger density of the AT25SF321B-SSHB-T simply provides more sectors and blocks within the same erase architecture, so firmware erase routines written for the AT25SF161B-SSHB-T remain structurally compatible.
Do these devices support security features such as a unique ID or protected sectors?
Yes. Both the AT25SF321B-SSHB-T and AT25SF161B-SSHB-T provide a 128-bit factory-programmed unique ID, a 64-bit OTP security register, and hardware/software write protection via the status register and /WP pin. These features are consistent across the AT25SF series and support secure boot and anti-cloning implementations.
Which part should be selected for a new design requiring 2 MB of code storage?
For a 2 MB requirement, the AT25SF161B-SSHB-T matches the needed density directly. The AT25SF321B-SSHB-T offers 4 MB and provides headroom for future firmware growth or data logging, at the cost of a larger die and potentially different pricing. Selection should be based on verified datasheet parameters, lifecycle status, and availability from authorized distributors such as DigiKey, Mouser, or Renesas directly.